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Emerging Technology 3-D Transistors - Essay Example

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This paper 'Emerging Technology 3-D Transistors' tells that makers of memory cells have been concerned with ways of making the life and performance of memory cells in various mobile devices more advanced. This has been done by particularly basing the functionality of these memory cells on transistors…
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Emerging Technology 3-D Transistors
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?Emerging Technology 3-D Transistors – For several years, makers of memory cells have been concerned with ways of making the life and performance of memory cells in various mobile devices more advanced and effective. This has been done by particularly basing the functionality of these memory cells on transistors. This is because transistors are in place to monitor energy efficiency and speed of processors. The better the transistor platform therefore, the better the overall output of a mobile device, as the device would have a highly advanced operational platform to process data inputs. It is in line with this that manufacturers of memory cells, particularly, Intel have been concerned with ways of enhancing the performance level of transistors that are mounted on memory cells for various mobile devices, particularly smart phones. The new technology that has emerged from Intel is 3-D transistors. 3-D transistors have been said to be a technical form of Tri-Gate that has been set to advance over the traditional two-dimension gate, which was in flat construction. With the advancement, the two-dimensional planar is replaced with three-dimensional silicon fin that ensures that the silicon substrate is raised up vertically. This emerging technology has been said to be necessary because it is no longer becoming possible to cram transistors in two-dimensional gates to make the Moore’s Law of doubling the number of transistors on a silicon device every two years possible. Keywords – processor; transistors; 3-D transistors; tri-gate; mobile device; memory cell; Moore’s Law; fin; silicon; advancement; dimensional; chips I. INTRODUCTION The cell phone industry has grown to heights that can be described as the most phenomenal in decades since the introduction of the technology. There are indeed a number of factors that have aided in the rapid growth of the cell phone industry, particularly due to the efficiency and effectiveness of the various components of technologies that come together to make up the holistic cell phone industry. One of such components of technologies that cannot be overlooked is the performances of cell phones that have made them versatile to performing a number of functions, including advanced memory cells. It would be noted however that the making and functionality of these memory cells are always based on the mounting of transistors (Han and Wentzlo, 2010). these transistors have always been in place to enhance energy efficiency and monitor the speed of processors, ensuring that the cell phones and other mobile technology devices can undertake processes input in them quite easily (Joyner, Zarkesh-Ha, and Meindl, 2001). With this function of transistors in mobile devices, it is very clear to note that these mobile devices including new forms of smart phones cannot be integrated with component array of functionalities if they do not have an effective transistor base to regulate energy efficiency and processor speed (Apte, Doering, and Gargini, 2007). It is in line with this that the focus of most memory cell makers has been on the need to enhance the efficacy of transistors. This paper serves as a survey paper to critically analyze the works of existing reviewers on a particular new technology in the line of transistors, which are 3-D transistors. Intel’s 3-D transistors are used as a model. II. SURVEY FINDINGS A. Intel’s Motivation to go 3-D Since the emergence of this 3-D transistors idea, transistors were generally mounted on 2-D platforms, called the 2-D planer 2-D gate (Dietrich and Haase, 2012). Various researchers have therefore tried to find out what the motivation of Intel to go 3-D could be. In this, it has been identified that the major motivation behind the emerging technology of 3-D transistors is Moore’s Law (Davis et al, 2005). Chang, Zuo, Wang, Yu, and Boning (2012) notes that Moore’s Law states that “the number of transistors per chip will double roughly every two years.” By implication, the memory cell that houses the chips must be in a position to accommodate the increasing numbers of transistors. By continuing to mount these increasing numbers of transistors on the 2-D platforms, the implication was that there was going to be cramming, which was going to affect the outcome of transistors as the provisional base of the 2-D planar gates never increased or gave room for more transistors (Garg and Marculescu, 2009). The 3-D therefore comes in as a Tri-Gate transistor that has the advantage of raising the silicon substrate vertically with the introduction of a thin three dimensional silicon fin (Drego, Chandrakasan, and Boning, 2007). According to Intel, the fin allows additional control, which makes it possible for there to be accumulated transistor current flowing when the transistor is put on (Karmarkar, 2009). There is also a minimization of power because the current flowing goes down to close to zero when the transistor power is put off. Also for the sake of performance, there is an easy switch between the two on and off states (Hess, 2007). The new 3-D transistor makes use of 22 nanometer and built in the exemplification below. Source: Intel B. Easing the Mobile Industry with 3-D Transistors The coming into force of the 3-D transistor has been found to be for the benefit of the mobile industry, particularly when it comes to the mobile phone industry with its advancements in smart phone technology (Perry et al, 2012). Patti (2006) notes that the smart phone industry has gotten to an era where the number of applications a mobile device can handle is a major competitive advantage for the market. But there is virtually no mobile platform that can handle as much application in its operating system if the core need for the memory cell to ensure enhanced processing speed is absent (Chang, Zuo, Wang, Yu, and Boning (2012). With the 3-D transistors therefore, the mobile industry will be eased of minimized application levels as the 3-D transistor has been identified to ensure guaranteed chip speed (Kim et al, 2012). Rabaey, Chandrakasan, and Nikolic (2013) has even argued that the benefit is not just going to be about the processing speed of chips but also to ensure more power-efficient designs. As a requirement, a raised processor speed, there should be provision for power management because processor speed is built dependent on power. In line with this, Intel has designed its emerging technology in such a manner that the 3-D transistors allow memory chips to function on lower voltage with minimal leakage (Dietrich and Haase, 2012). This way, there is the guarantee of both enhanced performance and energy efficiency if compared with existing chips from the same company. C. Market Potential of the Emerging Technology The emerging technology of 3-D transistors is expected to come with several market benefits in terms of market value and market share for Intel, especially in the smart phone and tablet markets. Studies show that Intel’s current competitor in terms of chips is ARM Holdings, which is a U.K based transistor maker for most smart phone and tablet making companies (Mick, Wilson, and Franzon, 2002). Currently, ARM chips are popular for the sake of its power efficiency. But with a 3-D transistor from Intel that works with 22nm planar transistors, there is the assurance that there will be 37% performance increase at low voltage (Pelgrom, Duinmaijer, and Welbers, 2013). Knowing that mobile devices such as smart phones and tablets operate on less energy due to their back and forth switching system, Intel is now in a better market position to compete as the 3-D transistors will guarantee both performance and energy management (Khan, Alam, and Hassoun, 2009). With 37% of performance enhancement, mobile device makers that switch to Intel’s 3-D transistors will be having the added advantage of building devices that will have the potential of accommodating more input activities that can easily be handled by the processor functionality of the 3-D transistors. For example, Intel reports that its 3-D transistors have the potential of consuming less power, which is up to half the power that is used to perform the same functions as 2-D planar transistors provide on 32nm chips (Kim et al, 2012). In effect, Intel now has a new marketing advantage if it uses this emerging technology as a differentiation strategic option to identify the differentiated needs of handheld device makers and trade with these. III. CHALLENGES Though a very excellent invention that guarantees higher market potential for Intel, the making of 3-D transistors have been said to be highly capital and labor intensive (Pelgrom, Duinmaijer, and Welbers, 2013). This means that the company is spending so much on the manufacturing of the products, which makes the unit price of each device quite expensive. The company is thus presented with the challenge of convincing its consumer and stakeholder base to appreciate the 3-D transistors from a differentiated strategic option viewpoint, where the product will be patronized for its value offers in terms of high performance rather than judging it from a cost leadership strategic option viewpoint. Into the future also, it is important for the company to guide against new entrant competition by establishing very formidable brand equity (Rabaey, Chandrakasan, and Nikolic, 2013). Such brand equity can only be realized if through constant research and development (R&D), the company is able to build on the processor efficiency and power management potentials of its transistors on a very constant basis. IV. CONCLUSION From the above findings, it can be concluded that Intel has made a very important discovery with its 3-D transistors emerging technology. This technology has indeed come to be of benefit to the larger mobile device users base, with more particular market focus for Intel and other developers. The need for advancement however ought to be pursued on a constant basis to ensure that there is rapid advancement of the new technology to suit the needs of future generations. References [1] P. Apte, B. Doering, and P. Gargini. The international technology roadmap for semi-conductors, 2007. [2] A.H. Chang, K. Zuo, J. Wang, D. Yu, and D. Boning. Test structure, circuits and extraction methods to determine the radius of infuence of STI and polysilicon pattern density. In 13th International Symposium on Quality Electronic Design, pages 185-192, 2012. [3] W.R. Davis, J. Wilson, S. Mick, J. Xu, H. Hua, C. Mineo, A.M. Sule, M. Steer, and P.D. Franzon. Demystifying 3D ICs: the pros and cons of going vertical. IEEE Design & Test of Computers, 22(6):498-510, 2005. [4] M. Dietrich and J. Haase, editors. Process Variations and Probabilistic Integrated Circuit Design. Springer Science+Business Media, 233 Sring St., New York, NY, 10013, USA, 2012. [5] N. Drego, A. Chandrakasan, and D. Boning. A test-structure to efficiently study threshold-voltage variation in large MOSFET arrays. In Proc. International Symposium on Quality Electronic Design, pages 281-286, 2007. [6] S. Garg and D. Marculescu. 3D-GCP: An analytical model for the impact of process variations on the critical path delay distribution of3D ICs. In International Symposium on Quality Electronic Design, 2009, pages 147-155, 2009. [7] S. Han and D.D. Wentzlo. Wireless power transfer using resonant inductive coupling for 3D integrated ICs. In IEEE International 3D Integration Conference, pages 1-5, 2010. [8] C. Hess, S. Saxena, H. Karbasi, S. Subramanian, M. Quarantelli, A. Rossoni, S. Tonello, S. Zhao, and D. Slisher. Device array scribe characterization vehicle test chip for ultra fast product wafer variability monitoring. In Proc. IEEE International Conference on Microelectronic Test Structures, pages 145-149, 2007. [9] J.W. Joyner, P. Zarkesh-Ha, and J.D. Meindl. A stochastic global net-length distribution for a three-dimensional system-on-a-chip (3d-soc). In 14th annual IEEE International ASIC/SOC Conference, pages 147-151, 2001. [10] A. P. Karmarkar. Performanace and reliability analysis of 3d-integration structures employing Through Silicon Via (TSV). In Reliability Physics Symposium, IEEE International, pages 682-687, 2009. [11] N.H. Khan, S.M. Alam, and S. Hassoun. Through-Silicon Via (TSV)-induced noise characterization and noise mitigation using coaxial TSVs. In IEEE International Conference on 3D System Integration, pages 1-7, 2009. [12] D. Kim, J Kim, J Pak, H. Lee, J. Lee, K. Park, and j. Kim. Vertical tree 3-dimensional tsv clock distribution network in 3D IC. In IEEE 62nd Electronics Components and Technology Conference, pages 1945-1950, 2012. [14] S. Mick, J. Wilson, and P. Franzon. 4 Gbps high-density AC coupled interconnection. In Proceedings of the IEEE Custom Integrated Circuits Conference, pages 133-140, 2002. [15] R. S. Patti. Three-dimensional integrated circuits and the future of system-on-chip designs. Proceedings of the IEEE, 94(6):1214-1224, 2006. [16] M. J. M. Pelgrom, A. C. J. Duinmaijer, and A. P. G. Welbers. Matching properties of MOS transistors. IEEE Journal of Solid-State Circuits, 24(5):1433-1440, 2013. [17] D. Perry, J. Cho, S. Domae, P. Asimakopoulos, A. Yakovlev, P. Marchal, G. Can der Plas, and N. Minas. An efficient array structure to characterize the impact of through silicon vias on FET devices. In IEEE International Conference on Microelectronic Test Structures, pages 118-122, 2012. [18] J.M. Rabaey, A. Chandrakasan, and B. Nikolic. Digital Integrated Circuits: A Design Perspective. Pearson Education, Inc., Upper Saddle River, NJ, 07458, USA, 2nd edition, 2013. Read More
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