Design of a 4-bit Universal Shift Register - Essay Example

?Assignment Table of contents Design of a 4-bit Universal shift register in VHDL using Xilinx ISE 2 Introduction 2 2.Design Overview 2 3.Design Solution 3 4.VHDL code listing 4 5.Result 6 6.Conclusion 11 1. Introduction 2 2. Design Overview 2 3. Design Solution 3 4. VHDL code listing 5 5. Result 6 6. Conclusion 11 Design of a 4-bit Universal shift register in VHDL using Xilinx ISE 1. Introduction A register in digital circuits is a memory element that is employed for storing and manipulating data. These registers are categorized based on how the information is retrieved or stored. A serial register operates serially, accepting and transferring data one bit at a time, while a parallel register operates on a parallel fashion accepting and transferring all the bits simultaneously. Since mere transferring or storing data in digital circuits is literally achieved by shifting the bits, the registers specifically used for storing and retrieval purposes without any manipulations, are called shift registers. A shift register is generally designed with a series of flip-flops connected in the form of a chain such that the output of one is connected to the input of the other expect the output of the last one which is the actual output of the circuit. A universal shift register is one that incorporates all the features that are applicable for shifting operations including parallel input/output, left/right-shift serial inputs, operating mode control inputs (S1 & S0) and direct overriding clear line (RESET), etc. 2. Design Overview For this assignment, a 4-bit universal shift register is designed in VHDL (VHSI Hardware Description Language) and simulated in VHDL IDE- Xilinx ISE. VHDL is generally used to write down the entire digital circuit description and its logic in the form of code or program. The circuit description is defined as entity and the logic as process. The process can be written using either of the 3 different approaches: structural which the individual components and internal signals are taken into consideration for describing the inputs and outputs, dataflow which relates the output to the input in terms of Boolean equations and behavioural which considers the actual behaviour of the circuit for designing. The schematic view of the circuit created in VHDL using Xilinx ISE is shown in the below fig: Fig 1. Schematic view of 4-bit universal Shift Register created in Xilinx ISE The input S1 and S0 act as control signals which determines the mode of operation of the shift register. The possible combination of the two signals along with the required mode of operation are summarised in the below table: S1 S0 Action 0 0 Hold (retain the previous state) 0 1 Shift left 1 0 Shift right 1 1 Parallel load 3. Design Solution Based on the above truth table for possible combinations of control signals, the state function table is derived for all combinations of input signals and control signals with respect to RESET and CLOCK signals and is summarised below: RESET Mode Clock Serial IN Parallel IN OUTPUTS _RST S1 S0 CLK SIL SIR D0 D1 D2 D3 Q3 Q2 Q1 Q0 0 X X X X X X X X X X X X X 1 X X Not ? X X X X X X Q3 Q2 Q1 Q0 0 0 0 ? X X X X X X Q3 Q2 Q1 Q0 0 0 1 ? 1 X X X X X Q2 Q1 Q0 1 0 0 1 ? 0 X X X X X Q2 Q1 Q0 0 0 1 0 ? X 1 X X X X 1 Q3 Q2 Q1 0 1 0 ? X 0 X X X X 0 Q3 Q2 Q1 0 1 1 ? X X D0 D1 D2 D3 Q0 Q1 Q2 Q3 X – don’t care condition ????low to high clock transition In order to achieve the above functionality using VHDL programming, behavioural approach of VHDL is employed in the process definition. This approach is chosen due to the fact that it is purely behaviour oriented and highly independent of the design implementations and will not change with changes in design approach for the same behaviour. The process is defined with the circuit’s behavioural architecture and the event attribute on the CLK signal is employed, to realize the clock signal state change. Since RESET signal is asynchronous and needs immediate action irrespective of the states of other inputs, RST is checked at the beginning of the process as a first step using an IF statement. Upon confirmation that the RST is not triggered, the various combinations of the control signal are checked using CASE statements in the ELSE loop. For the hold behaviour, NULL operator is employed in order to perform nothing thereby maintaining the states of the previous cycle. For the right and left shift behaviour, the bits are shifted right and left and concatenated with the corresponding SIR and SIL bits at the shifted ends. For the parallel operation, the bits are just sent out from D3-0 to Q3-0. 4. VHDL code listing A complete listing of the VHDL coding is given below: library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity shiftreg_vhdl is Port ( CLOCK : in STD_LOGIC; RESET : in STD_LOGIC; SIL : in STD_LOGIC; SIR : in STD_LOGIC; S : in STD_LOGIC_VECTOR (1 downto 0); D : in STD_LOGIC_VECTOR (3 downto 0); Q : INout STD_LOGIC_VECTOR (3 downto 0)); end shiftreg_vhdl; architecture Behavioral of shiftreg_vhdl is --- initialize the temp signal begin PROCESS (CLOCK,RESET) Begin -- RESET behaviour if RESET = '1' then Q Read More