The main purpose of this research of "Analog CAD" is to get the values of transistor sizes and components values like resistors and capacitances if the analog circuit specification is given. The optimization technique it adopts is geometric programming (Boyd, 2004). Till today analog circuit design automation is done for long length transistors or sub-micron transistors. Main objective of this research work is to automate circuit in deep sub-micron region. Before starting actual work on any topic it is necessary to go through literatures otherwise one may land up in a result which has already been found out by some other person.This section deals with the existing literatures related to analog circuit optimization. It outlines a summary of all the resource materials, authorial credentials, content credibility, source credibility, text credibility- Fluid integration of the source evaluation. A true literature review gives the proper sense of works that technology has achieved till date into that specified topic which helps one researcher to bring down his own research problem.Han Young et al. (1990) developed an analog silicon compilation system for CMOS op amps (OPASYN). The synthesis starts from a certain specification. From its database, program selects op amp topology that suits most with the given specification. Using parametric optimization the circuit then determines optimal value for its parameters. It also produces Design-Rule-Correct compact layout of the optimized op amp.
Yang et al. (1995) proposed a Simulated Annealing (SA) algorithm for topology selection and sizing. In analog cells, topology choice and sizing simultaneously is efficient than normal two step mode synthesis. Basic problem with that approach is that super circuits must be worked out for each sort of analog cells.
Chen et al. (2000) placed an iterative optimization idea for improving delay in digital circuit. Instead of only adjusting that gate sizes to reduce delay, they adjusted wire loads of the gates by repositioning them using geometric program. It gave better result in deep sub-micron design where the effect of interconnect delays dominates
Mandal P and Visvanathan V (2001) devised an efficient technique for sizing of op amp by sequential convex optimization problem. This method then prototyped in MATLAB to apply into CMOS two stage op amp. Paper mostly focuses on long length transistor. In short channel case results did not come satisfactory due to second order effects. To overcome this, model was used that gave acceptable result..
Hershenson M et al. (2001) also worked on same topic and came out with fruitful result. There they have used 0.8 technology.
Dawson et al. (2001), using geometric programming optimized the allocation of local feedback loops in a multistage amplifier. In a multistage amplifier local feedback loops effects its overall bandwidth, gain, rise time, noise and linearity. Using GP tool these problems had been solved taking into account wide variety of constraints.
After that, Daems et al. (2001) came with simulation based automatic generation of signomial and posynomial models that can be used for analog design automation. These posynomial models were found to be more useful for geometric programming optimization. There, they tested the methodology with a CMOS OTA in 0.7 m technology.
Hershenson M. (2002) presented a technique for the design of Analog- Digital Converter (ADC). In a predefined pipeline ADC topology she tried to get the component values and transistor sizes meeting the specification and keeping constraints like power, SNR, sampling frequency and area in convex form.
Eackelaert et al. (2003) depicted a new technique to generate symbolic expressions for the performance characteristics. The technique determines the coefficients and the exponents of a posynomial template based