Pentacene-Based Organic MIS Structures - Essay Example

Introduction to Pentacene Based Organic MIS Structures Several applications use organic electro-optics and electronic devices due to the revolutionary developments made in the organic thin film transistors (OTFT), organic light emitting devices (OLED), photo-detectors and photo-voltaic cells [1]. These organic electronic devices can be fabricated at low price and low temperature due to the flexible nature of the organic electronic materials, which are the conductive polymers, used in these devices, which is not attainable from their inorganic counterparts such as silicon, copper, etc. Conductive polymers such as Pentacene, Polyacetylene, Polyyaniline, etc are not only more flexible and less expensive in comparison to inorganic conductors but also lighter in weight than the inorganic electric conducting materials which are the traditional metals. In this paper, we will specifically discuss the molecular structure and the electronic properties of the organic metal-insulator-semi-conductor (MIS) structures which are based on the organic material called, Pentacene. Particularly, the efficiency of the pentacene field effect transistors (FET) due to its structural attributes have made it practicable to device applications which are mechanically flexible and in-expensive in the overall cost, with large space requiring for coverage [2]. Although, irrespective of the efficiency and great potential of the pentacene material, the performance of such organic MIS structures, which are based on pentacene, are confined to less efficiency since organic materials have high risk of defects and trap densities which result in the poor quality of the electronic devices and their materials [3]. Lin, Gundlach, Jackson and Nelson in their study of electron devices have shown that that the popular aromatic molecule, Pentacene has the field-effect mobilities to be about 1.5 cm2/Vs [4]. Furthermore, they suggested that by placing a self-organizing material between the dielectric SiO2-gate and the pentacene-active material, the characteristics of the pentacene thin film transistors (TFT) can be improved. This is because of the crystallinity, the interface defects and the traps taking place between the SiO2-gate dielectrics and the pentacene-active materials which subsequently effect the operations and performance of the TFT devices. The organic thin film transistors (OTFT) and the in-organic TFT are related to each other with respect to the primary function and design. In particular, OTFT is a device with three terminals in which flow of the current with respect to an applied bias, amidst the source and the drain electrode is controlled by the application of the voltage on the controls of the gate electrodes. Figure 1 provided below shows the basic schematic diagram for the field-effect transistor (FET), in which Vg is the voltage applied on the gate and Vds is the voltage applied on the source-drain. Figure 1 showing basic field effect transistor [6]. The mobility is the performance parameter represented by ‘µ’ which depicts the movement of the charge carriers in the active layer with respect to an electric field which is directly related to the switching speed of the FET. This value is obtained by measuring the current-voltage of the device and the larger be this value, the better would be the performance of the FET. The active layer in the organic transistors is composed of a thin film which comprises of the highly adjoined molecules called polymers such as the p-channel pentacene as shown in figure 2 provided below. Figure 2 showing the p-channel Pentacene molecular structure [6]. Organic materials pass current through the majority of the carriers without an inversion regime which is in contrast to their inorganic counterparts. The traps which change the levels of the energy and resists/stops the flow of the charge carriers are caused due to the impurities or the in-consistencies present in the molecular structure of these less-ordered organic materials. Literature Review Pentacene, C22H14 is the organic material that shows the highest hole and charge carriers mobility of the polymers. This material is known for its potential to build highly ordered organic thin films depending on the substrate and the growth conditions. These fabricated films are supported by the several low cost substrates. Department d’Enginyeria Electronica, Universitat Politecnica de Catalunya, Spain obtained the pentacene thin films in its original form on substrates of Corning glass 7059 with the help of the traditional thermal evaporator deposition technique at the maximum pressure of 10-6 mbar [15]. It was kept at the room temperature that is 25 oC while the deposition was taking place. The rate of the deposition was above 20 Å/s. The fabricated films have the thickness with in the range of 0.5-1.0 µm [15]. The Corning glass substrates were studied structurally and electrically. The resulting films were analyzed with the help of X-Ray diffraction (XRD) and Scanning electron microscopy (SEM) to determine the microstructure of the obtained pentacene samples. Figure 3 showing the X-Ray diffraction spectrum of a pentacene thin film which has been deposited on Corning glass with the thickness of 0.8 µm [15]. The X-ray diffraction spectrum of the pentacene thin film on Corning glass as shown in the above figure shows the presence of the two triclinic crystalline phases which are 00l k and 00l k’. The first order diffraction peak, 001’ at 5.75o describes the phase α which is also known as the thin film phase with the lattice spacing of 15.35 Å. The first order diffraction peak of 001 at 6.15o with the lattice spacing of 14.34 Å corresponding to the crystalline bulk phase of the material, describes the phase β. The literature on the subject reveals that the increase in the bulk crystalline phase is observed if the deposition rates are low that is below 1Å/s or the temperatures of the substrate are above 80 oC [15]. It has been observed that bulk crystalline phase has been contributed significantly in spite of the fact that these films were exposed at the room temperature under high deposition rates which is possible due to the thickness of the provided samples. Figure 4 showing the typical scanning electron microscope planar of a pentacene thin film on a Corning glass [15]. A typical scanning electron microscope planar of a pentacene thin film on a Corning glass as provided in the above figure clearly shows the small domains with diameters of 100 nm approximately. Several studies have been done in order to find out the case of increasing the electrical conductivity of the pentacene thin film with the help of iodine doping. It is known that pentacene can easily be doped by immersing it in to a solution that has been prepared with iodine and acetonitrile [15]. So, a solution is prepared by diluting 5mg of iodine in 300 ml of acetonitrile. Several pieces obtained from a single pentacene thin film sample were immersed in the prepared solution. Then the electrical conductivity of the pentacene was measured by thermally evaporating the coplanar gold lines on to the pentacene pieces. The results of this experiment are shown in the plot provided in the figure given below. Figure 5 showing the Room temperature dark conductivity of the doping series of pentacene. The thermal activation energy calculated from Arrhenius plot is shown in the inset of the above picture [15]. The above plot also shows the grown dark conductivity of the undoped piece of the pentacene sample which is found to be 3 x 10-7 Ω-1 cm-1 at room temperature. The dark conductivity increases by the magnitude of almost 2 orders when the pentacene sample is doped for just a few minutes. The maximum conductivity of the pentacene piece reached 4 x 10-5 Ω-1 cm-1 when it was dipped in the iodine solution for 1 minute. The conductivity of the piece was lowered to 2 x 10-6 Ω-1 cm-1 when it was kept immersed in the iodine solution for an hour. This sample piece looked a little porous may be because of the subsequent etching done by the iodine solution. Thermally activated behaviour was observed from the conductivity of all the pentacene samples in the doping experiment. The Arrhenius plot for the temperature range of 20 oC till 60 oC , calculated the values for this thermal activation energy which is clearly shown in the inset of the figure 5 provided above. Also, the figure 5 shows the activation energy of 0.3 eV for the undoped piece of the pentacene. This energy was lowered to 0.2 eV for most of the conductive doped samples. The sign of the thermo power ascertain that all of the sample pieces showed the p-type conduction. The doping experiment further reported that the lattice spacing was increased by 4 Å due to the absorption of iodine between the molecular layers of the pentacene pieces. Now, two unique rectifying structures with undoped pentacene, glass/SnO2 /pentacene/Al and glass/ZnO:Al/pentacene/Au, would be tested as elementary devices. For the ‘glass/SnO2/ pentacene/Al’, the rectifying contact is formed at the top aluminium contact and for the ‘glass/ZnO:Al/pentacene/Au’, it is formed at the bottom electrode ZnO:Al. Pentacene makes ohmic contact with SnO2 and Au [15]. Figure 6 showing the Current-voltage characteristics of the rectifying structures [15]. The above plot shows the corresponding current-voltage characteristics of the respective rectifying structures. The on/off ratios for both the diodes have been found between 2 and 3 in magnitude. The high deposition rate which was above 20 Å could have caused the subsequent inhomogeneities and pinholes which further might have resulted in high leakage currents for the negative voltages. The preliminary experiments failed to get diodes from doped pentacene and ZnO:Al which could have occurred because the bottom contact was deteriorated by the iodine diffusion [16]. Another study investigating the growth control pentacene thin films on SiO2 /Si reported that changing the evaporation flux rate and the substrate temperature reproducibly controls the grain structure. The atomic force microscopy (AFM) analysis of the film surface in this study concludes that the surface roughness is related to the growth condition and decreases significantly for the flat topped grains [17]. The report on ‘Pentacene based Organic Transistors’ by Dan Kolb recorded the conductivity for the pentacene films between 1.84 × 10−8 Ω−1 cm−1 and 7.49 × 10−8 Ω−1 cm−1. The report discussed the fabrication of the pentacene transistors using the thermal evaporation technique and thus, obtained the mobilities of about 0.03 cm2V−1s−1 [18]. A study on ‘Pentacene Thin Film Transistors with Polymeric Gate Dielectric’ reported good electrical performances for these devices with field effect mobilities of 0.01 cm2V−1s−1 and low threshold voltages of about -15 V. The atomic force microscopy (AFM) in this study showed that the surface morphology of the dielectric develops the microstructure of the pentacene layers [19]. Another paper on the ‘Pentacene Thin Film Transistors on Inorganic Dielectrics: Morphology, Structural Properties and Electronic Transport’ reports that the surface chemistry also strongly influences the growth of the pentacene material and its electronic properties [20]. The study on ‘Pentacene Devices and Logic Gates Fabricated by Organic Vapour Phase Deposition’ revealed that the electrical characteristics of the pentacene thin films exhibit high saturation mobilities of about 1.35 cm2/Vs with excellent characteristics even at high rate of depositions [21]. Thin Film Deposition Techniques Thin film deposition techniques are broadly divided in to two categories, chemical deposition and physical deposition which are also, further divided in to their sub-categories. As per the scope of this report, we will discuss the physical deposition techniques which fabricate the thin film of the solid by employing the mechanical or thermodynamic principles. The sub-categories of the physical deposition techniques of the thin film are given below. The thermal evaporation is the deposition technique that employs an electric resistance heater in order to melt down the material by increasing its vapour pressure to an appropriate range. This process is executed in a highly isolated environment so that the vapor reaches the substrate with out any resistance caused by the reaction with other gas phase atoms present in the chamber, Furthermore, the vacuum causes the reduction in the impurities formed by the residual gas in the chamber which ascertains that only the materials that have the high vapour pressure on comparison to that of the heating element reach the substrate with out contaminating the film. The e-beam evaporation uses an electron beam in order to heat the specimen which causes the evaporation process to take place. This is done with the help of an electron gun that heats a small spot on the source material. This technique deposits the material with the lower vapour pressure due to the non-uniform heating of the source. Multi layer coating are deposited in a single duty cycle by using the e-beam technique. The following components are used in this technique: e-beam evaporation gun, a system controller, power supply, crucibles for the evaporation material, materials for evaporation and the material to be coated. Sputtering deposition technique deposits the thin films of a material on to the substrate by the formation of the gaseous plasma from which the ions are accelerated in to the source material. The target that is the source material is destroyed by the arrival of the ions through the transfer of the energy and thus, it is discharged as neutral particles such as atoms or clusters of molecules. This emission of neutral particles takes place in straight line provided it is not hit by something in its path of travel. Quality of coating is determined by the measurement of its porosity, micro and macro hardness, content of oxide, roughness of the surface and bond strength. Usually, the increase in the velocities of the particles also improves the quality of the coating. Uniform application of the thin film to the flat substrate also improves the quality of the coating which is achievable with the help of spin coating procedure. Large size of the particles produces the coating of poor quality, thus the material should be milled to get the appropriate size range of the particles. Substrate Cleaning Substrate cleaning is the removal of a residue or particle in order to improve corrosion protection and adhesion by reducing or eliminating the contamination acquired during the process of fabrication. Residues should be cleaned with the help of green materials under secure conditions. Aqueous solutions are commonly and ideally used for this purpose since they can be used, treated and discharged easily. The process of removing organic contaminants involves: Covering the surface of the substrate with Acetone. Scrubbing the surface of the substrate thoroughly with the help of a scrub. Use IPA to completely rinse off the residues of the Acetone and the contaminants from the substrate. Use N2 gun to blow dry the substrate after cleaning. O2 plasma etching can also be used to remove organic films and residues from the substrate. RCA Clean is another procedure for substrate cleaning that removes organic, metallic and oxide contaminants from the substrate. It removes the insoluble in-organic contaminants from the substrate with the help of the 5:1:1 H2O: H2O2: NH4OH solution. To remove a thin silicon dioxide layer where metallic contaminants might gather, the RCA clean uses the dilute solution of 20:1 H2O:HF . For removing ionic and heavy metal atomic contaminants from the substrate, this procedure uses 6:1:1 H2O:H2O2: HCl solution. Piranha Clean is another substrate cleaning process that removes organic materials such as oil, photoresist, etc. This process is not applicable on aluminum. This process uses the mixture of 98% sulphuric acid (H2SO4) and 30% hydrogen peroxide (H2O2) in the volume ratios of 2-4:1 which is heated to 100oC to clean the substrate. Photolithography Photolithography is a process in which the geometric shapes on a mask are transferred to the surface of the substrate. Following steps are involved in this process. Substrate Cleaning: This is the first step in which the substrate is chemically cleaned to eliminate the particles and the organic, metallic, ionic impurities from the surface of the substrate. Barrier Layer Formation: The second step is to form the barrier layer such as the deposition of the silicon dioxide on to the surface of the substrate. Photoresist Application: The third step of the photolithography process is to apply the photoresist on to the surface of the substrate. In IC manufacturing, the photoresist coating is applied by means of the standard method of high speed whirling of the silicon substrate. This technique is called spin coating which forms a thin uniform layer on the surface of the substrate. There are two types of photoresist which are: positive resist and negative resist. The positive resist is the one in which only the underlying material that is to be removed is exposed to the UV light; developer solution is then used to remove the exposed part whereas in case of the negative resist, the part of the material that is required to be retained is exposed to the UV light and thus, only the unexposed parts are removed with the help of the developer solution. Soft Baking: This is the fourth step in which all the solutions are removed from the photoresist coating. Soft baking makes the photoresist coating to become photosensitive. Mask Alignment and Exposure: A mask is a square shaped glass plate which has a pattern emulsified with the metal film on one side. This mask is aligned with the substrate so that its pattern can be transferred on to the surface of the substrate. Development: A special solution called developer is used which removes some part of the photoresist due to the chemical reaction that is triggered by the solution. Hard Baking: This is the final step of the photolithography process that hardens the photoresist and improves its adhesion to the surface of the substrate. Metal semiconductor contact Metal semi-conductor contact is a point at which the metal and the semi-conductor meet each other or come in to contact. We cannot assume that such contacts will have resistance as low as that of the two metals connected to each other. Specially, a huge mismatch between the Fermi energy levels of the two (the metal and the semi-conductor) causes this contact to rectify the high resistance. This resistance can be reduced by selecting the suitable material and option for the metal semi-conductor contact to take place. The different options of the metal semi-conductor contacts are described below which are aimed to reduce the resistance. Ohmic Contact is the one in which the height of the Schottky barrier, fB, is either zero or negative. This is the contact in which the resistance is independent of the voltage. Tunnel Contact is the one which has the positive barrier at the point of contact of the metal and the semi-conductor. The semi-conductor used in this contact is highly doped which means that there is a thin barrier between the metal and the semi-conductor. Annealed and Alloyed Contact between the metal and the semi-conductor takes place when the deposited metals due to the high temperature in the fabrication of the ohmic contacts, either form an alloy with the semi-conductor or the high temperature anneal removes/reduces the barrier at the point of contact between the metal and the semi-conductor. Figure 10: Energy band diagram of the metal and the semiconductor before (a) and after (b) contact is made [14]. Figure 11: Energy band diagram of a metal-semiconductor contact in thermal equilibrium [14]. References 1. Y. -Y. Lin, D. J. Gundlach, S. F. Nelson, and T. N. Jackson, IEEE Trans. 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Pentacene Thin Film Transistors on Inorganic Dielectrics: Morphology, Structural Properties and Electronic Transport. Journal of Applied Physics, 93, 1 (2003). 21. C. Rolin, S. Steudel, K. Myny, D. Cheyns, S. Verlaak, J. Genoe and P. Heremans. Pentacene Devices and Logic Gates Fabricated by Organic Vapour Phase Deposition, Applied Physics Letters 89, 203502 (2006). Read More