Digital Electronic System Project - Report Example

DISPLAY REPORT Name Institution Instructor Date Introduction This project involves designing of an integrated circuit, which is expected to perform the function of a BCD decoder. The integrated circuit uses an LED display of seven segments in making a display of digits from zero to nine. Each one of the seven segments is represented by one of the input line that has the label of (a) up to (g). This project is also aimed at introducing an understanding of the language of VHDL that is useful in describing designed digital systems. It allows for an understanding of the manner in which designing, stimulation as well as synthesis of both simple and complex logical circuits using programmable logic. In this project, it is important to have a better understanding of the operating principles of the VHDL-based systems. A description of the VHDL system is important in the compilation and stimulation of the system design (Grout, 2008). The project involves stimulation of the design and once this is achieved, computer aided tools are utilised in synthesising the VHDL code. After synthesis of the in a hardware form has been achieved, the development and verification process takes place. The performance of this project is useful since it gives an appropriate roadmap with regard to the implementation and verification of more complex digital circuits. The project involves the demonstration of the manner in which functional specifications are entered in VHDL to offer a description of various design of digital electronic systems. When it comes to designing simple digital electronic systems, the compiler is capable of offering a simple format of the design a well as the generation of the circuit implementation for the coded architecture (Luecke, 2005). BCD to 7 Segment Mappings The BCD to 7 Segment Mappings demonstrates and describes the translation of various BCD inputs to seven segment decoder and then to seven segment LED display. From this completed tabulation of the outputs obtained, logic expressions for the Boolean were designed to assist in the construction of the digital integrated circuit (Paul, 2010). 7-segment display and BCD-to-Seven Segment Decoder BCD inputs segment outputs display D C B A a b c d e f g 0 0 0 0 1 1 1 1 1 1 0 0 0 0 1 0 1 1 0 0 0 0 0 0 1 0 1 1 0 1 0 0 1 0 0 1 1 1 1 1 1 0 0 1 0 1 0 0 0 1 1 0 0 1 1 0 1 0 1 1 0 1 1 0 1 1 0 1 1 0 0 0 1 1 1 1 1 0 1 1 1 1 1 1 0 0 0 0 1 0 0 0 1 1 1 1 1 1 1 1 0 0 1 1 1 1 0 0 1 1 A completed table indicating segment mappings and display of the BCD inputs In the truth table indicated above, the behaviour of the display integrated circuit driver is displayed with a seven outputs. Each output represented a segment. In the segment output section of the table, "1" output is a representation of the segments with active display whereas "0" output is a representation of the segments with inactive display. The behaviour of the integrated circuit display driver may be described through an indication of the by a truth table Boolean Expression D C B A a b c d e f g Display 0 0 0 0 1 1 1 1 1 1 0 “0” 0 0 0 1 0 1 1 0 0 0 0 “1” 0 0 1 0 1 1 0 1 0 0 1 “2” 0 0 1 1 1 1 1 1 0 0 1 “3” 0 1 0 0 0 1 1 0 0 1 1 “4” 0 1 0 1 1 0 1 1 0 1 1 “5” 0 1 1 0 0 0 1 1 1 1 1 “6” 0 1 1 1 1 1 1 0 0 0 0 “7” 1 0 0 0 1 1 1 1 1 1 1 “8” 1 0 0 1 1 1 1 0 0 1 1 “9” However, in real life situation there may be the provision of an appropriate showcase. In this case, Karnaugh Maps techniques are employed in obtaining simplified versions or format of Boolean Logic expressions indicating the manner in which each of the 7 segments should behave for the BCD inputs. “1” A + 0 = A “2” A +1 = 1 “3” A x 0 = 0 “4” A x 1 = A “5” A + A = A “6” A + A’ = 1 “7” A x A = A “8” A x A’ = 0 “9” (A’)’ = A The Boolean expressions obtained were simplified through the application of the Karnaugh Maps techniques.The simplification involved the development of the tools required in performing transition of complex representations (Grout, 2008). The Karnaugh map was developed through a systematic approach as indicated below The Karnaugh map was also applied in wide logic simplification VHDL Code An attempt at obtaining a VHDL code that describes the conversion of the BCD input to 7 segment decoder indicated the following; This is a representation for the use of IEEE standard logic codes (Luecke, 2005) BCD 2 LED ENTITY IS PORT FOR(D:IN STANDARD _ VECTOR _ LOGIC(3 DOWN TO 0); O:OUT STANDARD_ LOGIC_ VECTOR(6 DOWN TO 0)); END BCD 2 LED ARCHITECTURE RTL OF BCD 2 LED IS: START OPERATION (D) START CASE D IS WHEN "0000" => O O O O O O O O O O O Read More